1. Field of the Invention
This invention relates to a dynamic random access memory (DRAM) and more particularly to the construction of memory cells thereof.
2. Description of the Related Art
The integration density and memory capacity of a DRAM in which each memory cell is formed of one transistor and one capacitor are rapidly increased with the progress of fine patterning technique. Use of a stacked capacitor cell structure is known as a method of increasing the capacitances of capacitors in the DRAM.
FIG. 1 is a cross sectional view of the conventional stacked capacitor cell taken along a bit line direction.
In order to form the stacked capacitor cell, a field oxide film 502 serving as an element isolation region is formed on a P-type silicon substrate 501 by local oxidation of silicon. After this, a gate oxide film 503, gate electrode 504 and source/drain diffused regions 505 are formed to constitute a transfer transistor. Further, an interlevel insulator 506 is disposed on the resultant structure and a storage node electrode 508 with a film thickness of 3000 .ANG., for example, is formed of phosphorus doped polysilicon in a contact hole 507 formed in the interlevel insulator 506. In order to electrically connect the storage node electrode 508 to the source/drain diffused regions 505, phosphorus is generally ion-implanted into the substrate 501 and storage node electrode 508 to approximately 1.times.10.sup.16 cm.sup.-2 (dose).
Then, a plate electrode 510 is formed of phosphorus doped polysilicon to a film thickness of 3000 .ANG., for example, with a capacitor dielectric film 509 disposed between the plate electrode 510 and the storage node electrode 508 and the like so as to form a stacked capacitor. After this, an interlevel insulator 511 is formed on the resultant structure and a contact hole 512 is continuously formed in the interlevel insulators 511 and 506. A bit line which is connected to the drain region 505 via the contact hole 512 is formed of a molybdenum silicide film 513, for example.
The DRAM stacked capacitor cell is formed through the above manufacturing process.
When the DRAM having the above stacked capacitor cell is formed with a high integration density, the following problems may occur.
That is, since the contact hole 512 is formed after the transfer transistor is formed and the stacked capacitor cell is formed, and then the bit line is connected to the drain region 505, it is necessary to form a deep contact hole, thus increasing the step in level of the bit line.